Embodiments of the present invention relate to a block control device for a semiconductor memory and a method for controlling the same, and more specifically, to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device.
Presently, memory devices are largely classified into volatile DRAMs and non-volatile flash memories.
The DRAM adjusts a channel width of a lower gate in response to a voltage applied to the gate, forms a channel between a source terminal and a drain terminal, and enables a capacitor coupled to the source terminal to be charged with electrons or to be discharged. Thereafter, the DRAM reads the charging or discharging state, such that it can identify data of ‘0’ or of ‘1’.
The DRAM is a volatile memory device, such that it has a disadvantage in that it has to continuously recharge capacitors with electricity. If the DRAM is powered off, data in the DRAM is unavoidably lost because of a leakage current, resulting in a large amount of power consumption.
Therefore, the demand of non-volatile memory devices, that are capable of maintaining stored information even when the non-volatile memory devices are powered off, is rapidly increasing.
F-N tunneling occurs in a NAND flash memory because of a voltage applied to a control gate and a channel region, such that a floating gate is charged with electrons or is discharged through the F-N tunneling. In accordance with the NAND flash memory, there arises a variation in threshold voltage of a channel region according to the charging or discharging state. The NAND flash memory reads such a variation in threshold voltage so that it can identify data of 0 or of 1 according to the read variation result.
In order to overcome the shortcomings of DRAM and flash memory and implement a next-generation memory device having advantages of the DRAM and the flash memory, many research institutes and companies are conducting intensive research into next-generation memory devices.
Research fields of the next-generation memory devices have been diversified according to constituent materials of a cell used as a basic unit inside of the next-generation memory device.
That is, a representative example of the next-generation memory is a phase change memory that makes data of 0 or of 1 using a resistance difference generated when a phase change material is cooled upon receiving a current. In this case, the difference in resistance is generated according to whether the cooled phase change material is in a solid state or an amorphous state having high resistance.
In addition, PoRAM is a memory device based on bistability conductive characteristics generated when a voltage is applied to a conductive organic material. In this case, the bistability conductive characteristics indicate that high resistance and low resistance are present in the same voltage.
In addition, a ferroelectric memory has high remnant polarization characteristics when being powered on using unique characteristics of a ferroelectric substance, such that it is used as a memory device.
In the meantime, in order to satisfy the LPDDR2 specification, after a code corresponding to each command is input to a system, a first block address and a second block address (i.e., the last block address) are sequentially input to the system.
As a result, the LPDDR non-volatile memory controls states of all blocks present between the first block address and the last block address such that it can enable all the blocks to perform a command operation corresponding to a lock state, an unlock state, or a lock-down state.
Specifically, a product not based on a Joint Electron Device Engineering Council (JEDEC) standard of the LPDDR2 non-volatile memory receives only one address related to a block address, and it is necessary for the product to perform a block lock operation, a block unlock operation, or a block lock-down operation only in a block corresponding to the received address.
A memory region of the semiconductor memory device is divided into a large number of memory blocks, and each memory block enters any one of a block lock state, a block unlock state, and a block lock-down state according to a control signal of a block control command.
In this case, a programming operation, a data deletion operation, and an overwrite operation of the memory block of either the block lock state or the block lock-down state are limited.
The programming operation, the data deletion operation, and the overwrite operation of the memory block are allowed in the block unlock state.
For example, if 1024 memory blocks are present, 1024 block control command generation circuits are needed to command each memory block to enter a block lock state, a block unlock state, or a block lock-down state.
That is, it is necessary for the semiconductor memory device to include as many block control command generation circuits as the number of memory blocks, such that each block control command generation circuit needs to be reduced in size.
Specifically, in order to satisfy the specification of the LPDDR2 non-volatile memory, it is necessary for the memory to automatically operate so that lock states of all blocks present between the first block address and the last block address becomes one of the command code states (e.g., lock, unlock, and lock-down states).